Ingegneria Elettronica | DIGITAL ELECTRONICS

cod. 0612400031

DIGITAL ELECTRONICS

	0612400031
	DIPARTIMENTO DI INGEGNERIA INDUSTRIALE
	EQF6
	ELECTRONIC ENGINEERING
	2016/2017

PERCORSO COMUNE Cohort 2014/2015

	OBBLIGATORIO
	YEAR OF COURSE 3
	YEAR OF DIDACTIC SYSTEM 2012
	PRIMO SEMESTRE

TEACHING UNITS

	SSD	CFU	HOURS	ACTIVITY	TYPE OF ACTIVITY
	ING-INF/01	9	90	LESSONS	COMPULSORY SUBJECTS, CHARACTERISTIC OF THE CLASS

	Objectives
	THE COURSE AIMS TO GIVE THE STUDENT A BASIC KNOWLEDGE OF DIGITAL ELECTRONICS. HAVE ANALYZED THE CIRCUITAL TOPOLOGIES AND OPERATIONS OF THE LOGIC GATES ARE EXAMINED, BOTH IN MOS AND BIPOLAR TECHNOLOGY. TO THIS END, THE COURSE WILL INCLUDE A METHODOLOGICAL AND AN APPLICATION PART. THE METHODOLOGICAL PART IS DEVOTED TO THE STUDY OF THE MOST IMPORTANT ASPECTS OF THE CIRCUIT OPERATIONS, VIA ANALYTICAL MODELS, IN ORDER TO DERIVE THE MOST SIGNIFICANT PARAMETERS OF THE DIGITAL LOGICS. THE APPLICATION PART IS DEDICATED TO THE PERFORMANCE OF COMPUTER-AIDED EXERCISES IN ORDER TO ACQUIRE THE BASIC KNOWLEDGE OF CIRCUIT SIMULATORS AND CAD LAYOUT.

THE COURSE AIMS TO GIVE THE STUDENT A BASIC KNOWLEDGE OF DIGITAL ELECTRONICS. HAVE ANALYZED THE CIRCUITAL TOPOLOGIES AND OPERATIONS OF THE LOGIC GATES ARE EXAMINED, BOTH IN MOS AND BIPOLAR TECHNOLOGY. TO THIS END, THE COURSE WILL INCLUDE A METHODOLOGICAL AND AN APPLICATION PART. THE METHODOLOGICAL PART IS DEVOTED TO THE STUDY OF THE MOST IMPORTANT ASPECTS OF THE CIRCUIT OPERATIONS, VIA ANALYTICAL MODELS, IN ORDER TO DERIVE THE MOST SIGNIFICANT PARAMETERS OF THE DIGITAL LOGICS. THE APPLICATION PART IS DEDICATED TO THE PERFORMANCE OF COMPUTER-AIDED EXERCISES IN ORDER TO ACQUIRE THE BASIC KNOWLEDGE OF CIRCUIT SIMULATORS AND CAD LAYOUT.

	Prerequisites
	FOR THE BEST ACHIEVEMENT OF THE COURSE OBJECTIVES, THE STUDENTS MUST HAVE THE FOLLOWING PREREQUISITES, BEFORE THE COURSE BEGINS: BASIC MATHEMATICAL KNOWLEDGE, WITH PARTICULAR REFERENCE TO METHODS OF SOLVING DIFFERENTIAL EQUATIONS; KNOWLEDGE OF THE FUNDAMENTAL CONCEPTS OF ELECTRONICS; KNOWLEDGE OF THE FUNDAMENTALS OF LOGIC DESIGN; KNOWLEDGE OF ELECTRONIC DEVICES BJT AND MOSFET.

	Contents
	INTRODUCTION TO INTEGRATED DIGITAL CIRCUITS: HISTORICAL OVERVIEW, MOORE'S LAW, DESIGN FLOW OF INTEGRATED ELECTRONIC SYSTEM. MENTIONS ON THE ALGEBRA OF BOOLE; REPRESENTATION OF BOOLEAN FUNCTIONS. GENERAL CHARACTERISTICS OF THE LOGIC FAMILIES: STATIC AND DYNAMIC CHARACTERISTICS; FAN-IN, FAN-OUT. BIPOLAR LOGIC CIRCUITS: THE TTL CIRCUITS, WIRED-AND, OPEN-COLLECTOR. CML FAMILY AND LOGIC, TTL-ECL INTERFACE CIRCUITS. MOSFET SWITCH-LEVEL CIRCUIT, PARASITIC PARAMETERS. NMOS LOGIC CIRCUITS: EEMOS AND EDMOS CIRCUITS. CMOS LOGIC CIRCUITS: THE FCMOS FAMILY , THE PSEUDO NMOS FAMILY, CVS AND PASS-TRANSISTOR; DYNAMIC FAMILIES. LAYOUT OF CMOS CIRCUITS; TOOLS FOR CIRCUITAL SIMULATION (SPICE) CMOS COMPLEX LOGIC GATES: CIRCUITAL ARCHITECTURE AND SIZING. STATIC AND DYNAMIC LATCH AND FLIP-FLOP; VOLATILE AND NON-VOLATILE MEMORIES. SYNTHESIS OF FINITE STATE MACHINES. INTRODUCTION TO MICROCONTROLLERS.

Contents

INTRODUCTION TO INTEGRATED DIGITAL CIRCUITS: HISTORICAL OVERVIEW, MOORE'S LAW, DESIGN FLOW OF INTEGRATED ELECTRONIC SYSTEM.
MENTIONS ON THE ALGEBRA OF BOOLE; REPRESENTATION OF BOOLEAN FUNCTIONS.
GENERAL CHARACTERISTICS OF THE LOGIC FAMILIES:
STATIC AND DYNAMIC CHARACTERISTICS; FAN-IN, FAN-OUT.

BIPOLAR LOGIC CIRCUITS: THE TTL CIRCUITS, WIRED-AND, OPEN-COLLECTOR. CML FAMILY AND LOGIC, TTL-ECL INTERFACE CIRCUITS.
MOSFET SWITCH-LEVEL CIRCUIT, PARASITIC PARAMETERS.
NMOS LOGIC CIRCUITS: EEMOS AND EDMOS CIRCUITS.
CMOS LOGIC CIRCUITS: THE FCMOS FAMILY , THE PSEUDO NMOS FAMILY, CVS AND PASS-TRANSISTOR; DYNAMIC FAMILIES.
LAYOUT OF CMOS CIRCUITS; TOOLS FOR CIRCUITAL SIMULATION (SPICE)
CMOS COMPLEX LOGIC GATES: CIRCUITAL ARCHITECTURE AND SIZING.
STATIC AND DYNAMIC LATCH AND FLIP-FLOP; VOLATILE AND NON-VOLATILE MEMORIES.
SYNTHESIS OF FINITE STATE MACHINES.
INTRODUCTION TO MICROCONTROLLERS.

	Teaching Methods
	THE COURSE IS COMPOSED BY LECTURES, CLASS EXERCISES AND PRACTICAL LABORATORY WORK. IN THE CLASS EXERCISE HOURS, STUDENTS WILL BE ASKED TO PERFORM NUMERICAL EXERCISES ON THE TOPICS OF THE COURSE, WHILE LABORATORY ACTIVITIES WILL BE AIMED AT SIZING, DESIGN AND SIMULATION OF CIRCUITS WITH ASSIGNED SPECIFICATIONS TO GROUPS OF STUDENTS, THUS STRENGTHENING THE CAPACITY TO WORK IN TEAMS.

	Verification of learning
	THE ACHIEVEMENT OF THE COURSE AIMS WILL BE VERIFIED THROUGH A WRITTEN TEST AND AN ORAL INTERVIEW. TO PASS THE WRITTEN TEST, THE STUDENT MUST DEMONSTRATE A GOOD UNDERSTANDING OF THE MAIN CONCEPTS PRESENTED IN THE COURSE AND BE ABLE TO APPLY THE METHODS OF ANALYSIS. THE EVALUATION OF THE SCRIPT, WHICH WILL TAKE INTO ACCOUNT BOTH THE ACCURACY OF THE ANALYSIS AND THE QUALITY OF THE PRESENTATION, WILL BE DIVIDED IN THE CATEGORIES "GOOD, FAIR AND SUFFICIENT", WHICH ALLOW THE STUDENT TO ACCESS THE ORAL TEST, WHILE THE EVALUATION OF "WHOLLY INADEQUATE" DENIES THE ADMISSION. FOR A BETTER GRADUATION, THOSE WRITTEN TESTS THAT WILL BE EVALUATED AT THE LIMIT OF THE "ADEGUACY", WILL BE CATEGORIZED AS "INSUFFICIENT" AND ADMITTED “SUB-CONDITIONE” TO THE ORAL INTERVIEW, ATHOUGH THE MAXIMUM ACHIEVABLE SCORE WILL BE LIMITED TO 24/30. THE ORAL EXAMINATION SCORE WILL TAKE INTO ACCOUNT THE MATURITY OF THE STUDENTS ON THE COURSE TOPICS, THE QUALITY OF THE PRESENTATION, AND THE CRITICAL SENSIBILITY ON THE TOPICS. PRAISE WOULD OCCUR IN THE CASE OF WRITTEN TEST ASSESSED AT LEAST FAIR, AND ORAL EXAM THAT FULLY MATCHES THE EVALUATION CRITERIA.

Verification of learning

THE ACHIEVEMENT OF THE COURSE AIMS WILL BE VERIFIED THROUGH A WRITTEN TEST AND AN ORAL INTERVIEW. TO PASS THE WRITTEN TEST, THE STUDENT MUST DEMONSTRATE A GOOD UNDERSTANDING OF THE MAIN CONCEPTS PRESENTED IN THE COURSE AND BE ABLE TO APPLY THE METHODS OF ANALYSIS. THE EVALUATION OF THE SCRIPT, WHICH WILL TAKE INTO ACCOUNT BOTH THE ACCURACY OF THE ANALYSIS AND THE QUALITY OF THE PRESENTATION, WILL BE DIVIDED IN THE CATEGORIES "GOOD, FAIR AND SUFFICIENT", WHICH ALLOW THE STUDENT TO ACCESS THE ORAL TEST, WHILE THE EVALUATION OF "WHOLLY INADEQUATE" DENIES THE ADMISSION. FOR A BETTER GRADUATION, THOSE WRITTEN TESTS THAT WILL BE EVALUATED AT THE LIMIT OF THE "ADEGUACY", WILL BE CATEGORIZED AS "INSUFFICIENT" AND ADMITTED “SUB-CONDITIONE” TO THE ORAL INTERVIEW, ATHOUGH THE MAXIMUM ACHIEVABLE SCORE WILL BE LIMITED TO 24/30. THE ORAL EXAMINATION SCORE WILL TAKE INTO ACCOUNT THE MATURITY OF THE STUDENTS ON THE COURSE TOPICS, THE QUALITY OF THE PRESENTATION, AND THE CRITICAL SENSIBILITY ON THE TOPICS. PRAISE WOULD OCCUR IN THE CASE OF WRITTEN TEST ASSESSED AT LEAST FAIR, AND ORAL EXAM THAT FULLY MATCHES THE EVALUATION CRITERIA.

	Texts
	JAN M. RABAEY, ANANTHA CHANDRAKASAN, BORIVOJE NICOLIC "CIRCUITI INTEGRATI DIGITALI 2/ED. L'OTTICA DEL PROGETTISTA", PEARSON. J. P. UYEMURA, “INTRODUCTION TO VLSI CIRCUITS AND SYSTEMS”, WILEY B. RICCÒ, F. FANTINI, P. BRAMBILLA: “INTRODUZIONE AI CIRCUITI INTEGRATI DIGITALI”, ZANICHELLI TELETTRA.

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